The present invention relates mainly to a semiconductor device using polycrystalline silicon and, more particularly, a semiconductor device having a planar channel region.
Recently, as a result of the development of the integration technique, various portable appliances such as portable telephones and electronic pocket notebooks have come to be actually used.
This type of portable appliances each use a battery as its power source, in which case, in view of reducing the switching loss thereof, a power MOSFET is used as a switching element having a low breakdown voltage and a low resistance.
Further, in the case of this type of portable appliances, the power source voltage tends to be lowered in view of low power consumption and long useful life; and thus, the power MOSFET which is the switching element of such a portable appliance is required to have its ON resistance lowered.
As has been described above, a semiconductor device for switching is required to have its ON resistance lowered to such an extent that the semiconductor device can be used also for portable appliances etc.
On the other hand, as a switching semiconductor device with a low breakdown voltage of about 8V to 60V, lateral MOSFET is known.
FIG. 1 is a plan view showing the structure of this type of lateral MOSFET, and FIG. 2 is a sectional view taken along the line 2--2 in FIG. 1 and seen in the direction indicated by arrows. This type of lateral MOSFET is constituted in such a manner that, on the surface of a p-type semiconductor substrate 1, a p-type well layer 2 is selectively formed, and, on the p-type well layer 2, an n-type drain layer 3 is selectively formed. On the p-type well layer 2, an n-type source layer 4 is formed at a position spaced apart from the n-type drain layer 3.
On that portion of the p-type well layer 2 which lies between the n-type drain layer 3 and the n-type source layer 4, a gate insulation film 5 is formed. On the gate insulation film 5, a gate electrode 6 is formed. On the n-type drain layer 3, a drain electrode 7 is formed. On the p-type well layer 2 ad the n-type source layer 4, a source electrode 8 is formed.
This lateral MOSFET operates as follows:
If, when a positive voltage is applied to the drain electrode 7 and a negative voltage is applied to the source electrode 8, a positive voltage which is more positive than the voltage at the source is applied to the gate electrode 6, then that surface portion of the p-type well layer 2 which is adjacent to the gate insulation film 5 is inverted into the n conductivity type, and thus, electrons flow from the n-type source layer 4 to the n-type drain layer 3 through the inversion layer. That is, the element is brought into conduction.
In case such a lateral MOSFET is used for the switching of a large current, it is important in view of suppressing the loss to hold down the resistance (ON resistance) in the ON state of the lateral MOSFET. Here, the ON resistance of the lateral MOSFET is, for the most part, the resistance of the channel portion 109. Due to this, in order to decrease the ON resistance of the lateral MOSFET, the width of the channel thereof should be enlarged. However, if the channel width is enlarged, the area occupied by the lateral MOSFET is increased.
Further, in the case of a lateral MOSFET having a low breakdown voltage of, e.g. 30V, the ON resistance thereof is about 40 .OMEGA..multidot.mm.sup.2 ; and, any further decrease of the ON resistance has its limit.
As has been described above, in the case of a lateral MOSFET, there is the problem that, if the channel width is widened, the area occupied by the element is increased.
Further, in the case of a lateral MOSFET, current flows through only the surface thereof; and thus, there is a limit to the reduction of the ON resistance thereof.
Next, a description of a semiconductor device of the vertical trench structure will be described below. FIG. 3 is a sectional view showing the structure of a vertical trench type semiconductor device. This semiconductor device is constructed in such a manner that, on an n+ type substrate 11 composed of monocrystalline silicon, an n- type base layer 12 is formed, and, in the surface of the n- type base layer 12, a p-type base layer (well) 13 is formed. In the surface of the p-type base layer 13, an n+ type source layer 14 is selectively formed. In the surface of the n+ type source layer 14, trenches 15 are selectively formed extending to a depth reaching the n-type substrate 11. In the respective trench 15, a gate electrode 17 is buried through an insulation film 16. On the surface of this semiconductor layer, an insulation layer 18 is selectively formed so as to expose the p-type base layer 13 and the n+ type source layer 14 in the vicinity thereof.
A source electrode 19 is formed so as to be contacted with the surface portions of the p-type base layer 13 and the n+ type source layer 14 which portions lie between the insulation layers. Further, on the opposite surface, with reference to the source electrode 19, of the n+ type substrate 11, a drain electrode 20 is formed.
The MOSFET of such a vertical trench structure, the interval W between the trenches becomes 2 .mu.m at the minimum. Such a MOSFET is formed in such a manner that, in order to prevent the operation of the parasitic npn transistor, the source electrode 19 is formed in a state contacted with both of the n+ type source layer 14 and the p-type base layer 13 so as to electrically short-circuit the two layers to each other.
Further, FIG. 4 shows the n+, n- n+ structure which is the structure obtained by omitting the p-type layer from the structure shown in FIG. 3. However, the n+ n- n+ structure has the defect that the breakdown voltage is lowered since the provision of a wider trench interval W is necessary.
For instance, in case a MOSFET of the n+ n- n+ structure is composed of monocrystalline silicon, there arises the problem that, even if the trenches are formed with a narrow trench interval of 0.5 .mu.m or less, the holes generated in the depletion layer are accumulated in the n- type base layer 12 to cause a parasitic bipolar operation, so that the breakdown voltage is deteriorated. Due to this, the breakdown voltage is lower than in the case the MOSFET is composed of polycrystalline silicon.